FIG. 1 of the drawings shows a conventional circuit arrangement comprising a differential pair of transistors Q1 and Q2. A circuit arrangement such as that shown in FIG. 1 may be used in an amplifier or a digital-to-analog converter (DAC). The transistors Q1 and Q2 receive complementary input voltages V and V at their bases, the voltages V and V swinging about a reference potential level V.sub.0. The collectors of the transistors Q1 and Q2 are connected through a load network to a reference potential level V.sub.CC, and the emitters of the transistors Q1 and Q2 are connected to the collector of a current source transistor Q3, which has its emitter connected to a reference potential level V.sub.EE. The base of the transistor Q3 is connected to a high gain feedback bias amplifier and draws a constant current or a desired value, dependent on the ratio of the resistance values of the resistors R.sub.E and R.sub.3, from the emitters of the transistors Q1 and Q2. The reference potential level V.sub.0 lies between the potential levels V.sub.CC and V.sub.EE. The output of the differential pair may be taken from the collectors of the transistors Q1 and Q2 and applied to a differential amplifier A, or alternatively a single-ended output may be taken from the collector of one of the transistors Q1 and Q2. Parasitic capacitances are associated with the collector of the transistor Q3. Therefore, when the differential input voltage changes, and brings about a change in the voltage V.sub.1 at the emitters of the transistors Q1 and Q2, a displacement current proportional to dV.sub.1 /dt is drawn from the emitters of the transistors Q1 and Q2. The displacement current is distributed between Q1 and Q2 in dependence upon the values of V and V. This capacitive displacement current causes perturbations in the output signal and increases settling time. This is particularly disadvantageous in the case of a DAC, because it increases the duration of the conversion cycle.
Moreover, when the voltage at the base of the transistor Q1 changes, charge is injected into the load network through the parasitic base/collector capacitance C.sub.jcl, and this causes a transient at the collector of the transistor. The voltage transients at the collectors of the transistors Q1 and Q2 are in opposite senses, and therefore they are added when the collector voltages are combined by the differential amplifier A.